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SY89297U 2.5/3.3v, 3.2gbps precision cml dual-channel programmable delay precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com december 2011 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 general description the SY89297U is a dc-3.2gbps programmable, two- channel delay line. each channel has a delay range from 2ns to 7ns (5ns delta delay) in programmable increments as small as 5ps. the delay step is extremely linear and monotonic over the entire prog ramming range, with 15ps inl over temperature and voltage. the delay varies in discrete steps based on a serial control word provided by the 3-pin serial control (sdata, sclk, and sload). the control word for each channel is 10-bits. both channels are programmed through a common serial interface. for increased delay, multiple SY89297U delay lines can be cascaded together. the SY89297U provides two independent 3.2gbps delay lines in an ultra-small 4mm x 4mm, 24-pin qfn package. for other delay line solutions, consider the sy89295u and sy89296u single-channel delay lines. evaluation boards are available for all these parts. datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . precision edge ? features ? dual-channel, programmable delay line ? serial programming interface (sdata, sclk, sload) ? guaranteed ac performance over temperature and voltage: ? > 3.2gbps/1.6ghz f max ? programming accuracy: ? linearity: ? 15ps to +15ps inl ? monotonic: ? 5ps to +25ps ? resolution: 5ps programming increments ? low-jitter design: 1ps rms typical random jitter ? programmable delay range: 5ns delay range ? cascade capability for increased delay ? flexible voltage operation: ? v cc = 2.5v 5% or 3.3v 10% ? industrial temperature range: ? 40c to +85c ? available in 24-pin (4mm x 4mm) qfn applications ? clock de-skewing ? timing adjustments ? aperture centering ? system calibration markets ? automated test equipment ? digital radio and video broadcasting ? closed caption encoders/decoders ? test and measurement
micrel, inc. SY89297U december 2011 2 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish SY89297Umg qfn-24 industrial 297u with pb-free bar line indicator pb-free nipdau SY89297Umgtr (2) qfn-24 industrial 297u with pb-free bar-line indicator pb-free nipdau notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 24-pin qfn truth tables inputs outputs ina, inb /ina, /inb qa, qb /qa, /qb 0 1 0 1 1 0 1 0 table 1. inputs/outputs /ena, /enb q, /q (a, b) 1 q = low, /q = high 0 in, /in delayed (normal operation) table 2. input enable (latches outputs)
micrel, inc. SY89297U december 2011 3 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 functional block diagram
micrel, inc. SY89297U december 2011 4 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 1 2 ina /ina channel a differential input: ina and /ina pins receive the channel a data. qa and /qa are the delayed product of ina and /ina. each input is internally terminated to vta through a 50 ? resistor (100 ? across ina and /ina). 3 vta input a termination center-tap: each side of the differential input pair terminates to this pin. this pin provides a center-tap to a terminatio n network for maximum interface flexibility. see ?input interface applications? section. 4 vtb input b termination center-tap: each side of the differential input pair terminates to this pin. this pin provides a center-tap to a terminatio n network for maximum interface flexibility. see ?input interface applications? section. 5 6 inb /inb channel b differential input: inb and /inb pins receive the channel b data. qb and /qb are the delayed product of inb and /inb. each input is internally terminated to vtb through a 50 ? resistor (100 ? across inb and /inb). 7 vref-ac reference voltage output: for ac-coupled input signals, this pin can bias the inputs in and /in. connect vref-ac directly to the vt input pin for each channel. de-couple to v cc using a 0.01f capacitor. maximum sink/source current is 0.5ma. for dc-coupled input applications, leave vref-ac pin floating. 8, 11, 20 gnd, exposed pad negative supply: exposed pad must be connected to a ground plane that is the same potential as the ground pins. 9 /ena cmos/ttl-compatible enable input: when the /e na pin is pulled high, qa is held low and /qa goes high after the programmed delay propagates through the part. /ena contains a 67k pull-down resistor and defaults low when left floating. logic threshold level is v cc /2 10 /enb cmos/ttl-compatible enable input: when the /e nb pin is pulled high, qb is held low and /qb goes high after the programmed delay propagates through the part. /enb contains a 67k pull-down resistor and defaults low when le ft floating. logic threshold level is vcc/2 12, 15, 16, 19 vcc power supply: bypass each supply pin with 0.1f//0.01f low-esr capacitors. see dc electrical characteristics table for more details. 2.5v 5% or 3.3v 10%. 13 14 /qb qb cml differential output: qb and /qb are the del ayed product of inb, /inb. cml outputs are terminated at the destination with 100 ? across the pair. see ?cml output termination? section. 17 18 /qa qa cml differential output: qa and /qa are the del ayed product of ina, /ina. cml outputs are terminated at the destination with 100 ? across the pair. see ?cml output termination? section. 23 22 sclk sdata cmos/ttl-compatible 3-pin serial programming co ntrol inputs: the 3-pin serial control sets each channel?s in to q delay. da(0:9) control channel a delay. db(0:9) control channel b. to program the two channels, insert a 20-bit word (da0:da9 and db0:db9) into sdata and clock in the control bits with sclk. maximum input frequency to sclk is 40mhz. data is loaded into the serial registers on the l-h transition of sc lk. after all 20-bits are clocked in, sload latches the new delay bits. these pins have internal pull-downs at the inputs. see ?ac electrical characteristics? for delay values. logic threshold level is vcc/2. sclk and sdata contain a 67k pull-down resistor and default low when left floating. 24 sload cmos/ttl-compatible 3-pin serial programming co ntrol input: sload controls the latches that transfer scanned data to the delay line. these la tches are transparent when sload is high. data transfers from the latch to the delay li ne on a l-h transition of sload. sload has to transition h-l before new data is loaded in the scan chain. when sload is high, the latches are transparent and sclk cannot switch. otherwise , new data will immediately transfer to the scan chain. logic threshold level is vcc/2. sload contains a 67k ? pull-down resistor and defaults low when left floating. 21 sout cmos/ttl-compatible output: this pin is used to support cascading multiple SY89297U delay lines. serial data is clocked into the sdata input and is clocked out of sout into the next SY89297U delay line. sout pin includes an internal 550 ? pull-up resistor.
micrel, inc. SY89297U december 2011 5 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) .................................. ?0.5v to +4.0v input voltage (v in ) .......................................... ?0.5v to v cc cml output voltage (v out )? ....... v cc ? 1.0v to v cc +0.5v current (v t ) source or sink current on vt pin ..................... 70ma input current source or sink curr ent on (in, /in) .................. 35ma current (v ref ) source or sink current on v ref-ac (2) ................ .0.5ma maximum operating juncti on temperature ............ 125c lead temperature (solde ring, 20sec.) ..................... 260c storage temperature (t s ) ....................... ?65c to +150c operating ratings (3) supply voltage (v cc ) t a ( ? 40 c to + 85 c) ................ +2.375v to +2.625v t a ( ? 40 c to + 75 c) .......................... +3.0v to 3.6v ambient temperature (t a ) .......................... ? 40c to +85c package thermal resistance (4) qfn ( ja ) still-air ............................................................... 43c/w qfn ( jb ) junction-to-board ........................................... 30.5c/w dc electrical characteristics (5) t a = ? 40c to +85c, channels a and b, unless otherwise stated. symbol parameter condition min. typ. max. units v cc power supply voltage range t a : ? 40c to +85c 2.375 2.5 2.625 v t a : ? 40c to +75c 3.0 3.3 3.6 v t a : ? 40c to +85c, airflow = 500 lfpm 3.0 3.3 3.6 v i cc power supply current maximum v cc , both channels combined, output load included 195 250 ma r in input resistance (in-to-vt, /in-to-vt) 45 50 55 ? r diff_in differential input resistance (in-to-/in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ?0.1 v v in input voltage swing (in, /in ) see figure 5a 0.1 1.0 v v diff_in differential input voltage swing (|in - /in|) see figure 5b 0.2 v v ref-ac output reference voltage v cc ?1.3 v cc ?1.2 v cc ?1.1 v v t_in voltage from input to v t 1.28 v notes: 1. permanent device damage may occur if ?abs olute maximum ratings? are exceeded. this is a stress rating only and functional op eration is not implied at conditions other than those deta iled in the operational sections of this data sheet. exposure to ?absolute maximum r ating? conditions for extended periods may affect device reliability. 2. due to the limited drive capability, use for input of the same package only. 3. the data sheet limits are not guaranteed if the dev ice is operated beyond the operating ratings. 4. thermal performance on qfn packages assumes exposed pad is soldered (or equivalent) to the device most negative potential (g nd). 5. the circuit is designed to meet the dc specifications shown in the table a fter thermal equilibrium has been established.
micrel, inc. SY89297U december 2011 6 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 cml outputs dc electrical characteristics (6) v cc = +2.5v +5% or +3.3v 10%, r l = 100 ? across the outputs; t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min. typ. max. units v oh output high voltage r l = 50 ? to v cc v cc ? 0.020 v cc ? 0.010 v cc v v out output voltage swing see figure 5a 325 400 mv v diff_out differential output voltage swing see figure 5b 650 800 mv r out output source impedance 45 50 55 ? lvttl/cmos dc electri cal characteristics (6) v cc = +2.5v +5% or 3.3v 10%, t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min. typ. max. units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current v ih = vcc 150 a i il input low current v il = 0.8v 50 a v ol output low voltage sout pin; i ol =1ma 0.55 v output high leakage current sout = v cc 100 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. ac electrical characteristics (7) t a = ? 40c to +85c, channels a and b, unless otherwise stated. symbol parameter condition min. typ. max. units f max maximum operating frequency clock: v out swing >200mv pk 1.6 ghz nrz data 3.2 gbps t pd propagation delay in to q; d[0?9]=0 in to q; d[0?9]=1023 /en to q: d[0?9]=0; v th = v cc /2 sdata to sout (d0?d9=low), no load 1000 5500 1000 2000 2000 7500 2500 4500 ps t range programmable range t pd (max) ? t pd (min) 4150 5115 ps t skew duty cycle skew t phl ? t plh note 8 45 55 %
micrel, inc. SY89297U december 2011 7 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (7) t a = ? 40c to +85c, channels a and b, unless otherwise stated. symbol parameter condition min. typ. max. units t step delay d0 high d1 high d2 high d3 high d4 high d5 high d6 high d7 high d8 high d9 high d0-d9 high 5 10 20 40 80 160 320 640 1280 2560 5115 ps monotonic ? 5 25 inl integral non-linearity note 9 ? 15 +15 ps t s setup time sdata to sclk sclk to sload /en to in note 10 note 11 400 400 300 ps t h hold time sload to sclk in to /en sclk to sdata note 12 note 13 300 ? 100 200 ps t pw pulse width sload 1000 ps t r release time /en to in note 14 800 ps t jitter cycle-to-cycle jitter total jitter random jitter note 15 note 16 note 17 2 20 2 ps rms ps pp ps rms t r , t f output rise/fall time 20% to 80% (q) 30 55 80 ps duty cycle input frequency = 1.6ghz 45 55 % notes: 7. high frequency ac electricals are guar anteed by design and characterization. 8. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of t he output. 9. inl (integral non-linearity) is defined from its corresponding point on the ideal delay versus d[9:0] curve as the deviation from its ideal delay. the maximum difference is the inl. theoretical ideal linearity (til) = (measured maximum del ay ? measured minimum delay) 1023. in l = measured delay ? (measured minimum delay + (step number x til)). 10. sclk has to transition l-h a setup time before the sload h- l transition to ensure the valid data is properly latched. see t iming diagram "setup and hold time: sclk and sload.? 11. this setup time is the minimum time that /en must be assert ed prior to the next transition of in / /in to prevent an output response greater than 75 mv to that in or /in transition. see timing diagram setup, hold and release time: in and /en." 12. sclk has to transition l-h a hold time after the sload h- l transition to ensure that the valid data is properly latched bef ore starting to load new data. see timing diagram "setup and hold time: sclk and sload.? 13. this hold time is the minimum time that /en must remain asserted after a negative going transition of in to prevent an outp ut response greater than +75mv to the in transition. see timing diagram ?setup, hold, and release time: in and /en.? 14. this release time is the minimum time that /en must be de-asserted prior to the next in / /in transition to affect the prop agation delay of in to q less than 1ps. see timing diagram ?setup, hold, and release time: in and /en.? 15. cycle-to-cycle jitter definition: the variation of periods between adjacent cycles over a random sample of adjacent cycle p airs. t jitter_cc = t n ? t n +1, where t is the time between rising edges of the output signal. 16. total jitter definition: with an ideal clock input, no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to- peak jitter value. 17. random jitter definition: jitter that is characteriz ed by a gaussian distribution, unbounded and is quantified by its sta ndard deviation and mean. random jitter is measured with a k28.7 comma defect pattern, measured at 1.5gbps.
micrel, inc. SY89297U december 2011 8 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 timing diagrams figure 1. setup and hold time: sdata and sclk figure 2. setup and hold time: sclk and sload
micrel, inc. SY89297U december 2011 9 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 timing diagrams (continued) figure 3. set-up, hold, and release time: in and /en figure 4. sload pulse width (tpw)
micrel, inc. SY89297U december 2011 10 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = +2.5v, gnd = 0v, v in = 100mv, r l = 100 ? across the outputs, t a = 25c. phase noise chart v cc = +2.5v, gnd = 0v, v in = 100mv, r l = 100 ? across the outputs, t a = 25c. f c : 1ghz delay setting: 00001 00110 (2ns)
micrel, inc. SY89297U december 2011 11 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 functional operati ng characteristics v cc = 2.5v or 3.3v, gnd = 0v, v in = 100mv, r l = 100 ? across the outputs, t a = 25c, maximum delay (d0 ? d9 = high).
micrel, inc. SY89297U december 2011 12 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 single-ended and di fferential swings figure 5a. single-ended voltage swing figure 5b. differential voltage swing input and output stages figure 6. input stage figure 7. cml output stage
micrel, inc. SY89297U december 2011 13 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 input interface applications option: may connect v t to v c c figure 8a. cml interface (dc-coupled) figure 8b. cml interface (ac-coupled) figure 8c. lvpecl interface (ac-coupled) figure 8d. lvpecl interface (dc-coupled) figure 8e. lvds interface (dc-coupled)
micrel, inc. SY89297U december 2011 14 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 cml output termination figure 9a. cml ac-coupled termination - 100 ? differential figure 9b. cml ac-coupled termination - 50 ? to v cc figure 9c. cml ac-coupled termination - 50 ? to v bias
micrel, inc. SY89297U december 2011 15 m9999-120211-c hbwhelp@micrel.com or (408) 955-1690 package information 24-pin (4mm x 4mm) qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2008 micrel, incorporated.

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